The present embodiments relate to electronic circuits and are more particularly directed to an integrated circuit with a dynamically controlled voltage supply.
Electronic circuits are prevalent in numerous applications and are used in devices in personal, business, and other environments. Demands of the marketplace affect many design aspects of these circuits, including device size, complexity, efficiency, performance, and cost. These aspects are often important in various devices. By way of example, the mobile phone industry is transitioning from devices that are voice oriented to devices that are multimedia oriented, and multimedia applications typically integrate high performance processing cores. As a result, the above-mentioned aspects of size, complexity, efficiency, performance, and cost manifest themselves in various areas, including energy consumption, speed capability, and battery lifetime. These areas are also a concern in various other electronic devices, particularly where energy is a concern such as in other battery-powered applications. Thus, to maintain pace with marketplace demands and supplier goals for these devices, considerations with respect to these factors are of paramount interest. The preferred embodiments are directed to these aspects.
With the developments described above, integrated circuit, or “chip”, design in the current state of the art often uses various criteria to determine a nominal level of voltage supply for the device, with a corresponding clock speed specification then determined from that nominal voltage supply. For example, some manufacturers develop a yield distribution curve, often in the shape of a Gaussian distribution (i.e., bell curve). Due to manufacturing variations, each chip in a group of chips will fall somewhere along this curve in terms of the quality of the overall silicon of the device. With this curve, for purposes of developing a speed specification for the entire group of chips, the weakest acceptable device is then tested with a power supply providing a voltage at which the device is predicted to perform over an acceptable period of time. For example, in current technology, such voltage may be on the order of 1.1 volts for a device, such as a digital signal processor, to operate reliably for a predicted period of seven years (where the use of seven years is only by way of example). This voltage, often referred to as the nominal voltage, is typically determined from various attributes of the device, such as the voltage susceptibility of the transistor gate oxides (or insulators) on the chip, as if often constrained by the gate oxide thickness. Thus, this nominal voltage becomes a constraint on the amount of voltage applied to all chips in the group. Moreover, once this nominal voltage is determined, it is used to determine the speed at which the weakest chip in the group can reliably perform, as further detailed below.
With the preceding, the present inventors recognize various drawbacks in the ultimate test-yielded speed specification that arises from testing a device with the nominal voltage, due to various allowances that must be made for variations and losses in the applied voltage. In one of these respects, the chip's voltage supply typically is a device external from the chip, and that voltage supply has a corresponding level of tolerance. For example, a voltage supply may be said to provide 1.1 volts, with a tolerance of 10%. Thus, the actual voltage provided by the supply may be anywhere in the approximate range of 1.0 volts to 1.2 volts. Accordingly, with the above voltage application and speed specification procedure, often the chip designer is required to assume a worst case scenario in terms of potential supply voltage, meaning in the present case the minus 10% voltage tolerance and a resultant output of the voltage supply of only 1.0 volts. In another respect, the prior art approach contemplates voltage loss between the power supply and the ultimate transistors of the chip's processing core(s). For example, the voltage supply as provided external from the chip traverses conductors between the voltage supply and the chip and they impart line losses due to the various attributes of the conductor lines (e.g., trace resistance and their tolerances). As another example, there may be line losses and tolerances internal to the chip, where those losses are incurred as the voltage is routed from the chip's external pins to the transistors of the chip's processing core(s). As still another example, temperature variations may cause a resistance change and, hence, a change in the voltage that ultimately reaches the chip's processing core(s).
As a result of the preceding, in the prior art the designer that is to determine a clock speed specification is often required to account for the worst case scenario for all of the possible voltage losses, by testing the corresponding chip core at a supply voltage level that includes all those losses. For instance, with a nominal voltage of 1.1 volts, then with these additional considerations there could be a worst-case-scenario loss of 0.2 volts before that nominal voltage reaches the processing core(s), coupled with the example above of 0.1 volt loss from the power supply tolerance. In this case, only 0.8 volts actually reaches the processing core(s). Thus, the designer applies this worst-case 0.8 volts directly to the chip core and evaluates the speed of operation that the core can reliably provide at that voltage. Of course, this speed will be less than that which would be achieved in an ideal (i.e., lossless) case, where 1.1 volts would be applied to the core. Thus, this resulting test-speed becomes the specification speed for the device. Hence, assuming the device is then used properly per its specification, it is thereafter implemented into a system by a vendor, installer, OEM or the like, and clocked at this worst-case speed while connected to the corresponding nominal voltage (e.g., 1.1 volts). Lastly, note that in one approach, a voltage supply with a smaller tolerance may be used so as to gain back some of the difference in test-confirmed clock speed as between the ideal case and the higher tolerance case, but of course a lower tolerance voltage supply is more costly and thereby increases the overall system cost.
As a final consideration with respect to the preceding, note that the prior art worst-case-scenario approach is often used to define the nominal voltage and test-confirmed clock speed as specifications for all chips in a group. Thus, chips in the same group, but that are better silicon than the weakest silicon device or that incur lesser losses than that anticipated in the worst-case scenarios, are necessarily constrained to perform at the test-confirmed clock speed in response to the nominal voltage as determined based on worst case conditions including the lesser performing chip. Thus, the above-described limitations are imposed on entire groups of chips rather than just single tested chips.
In view of the above, there is a need to further improve aspects relating to circuit and device performance control and energy efficiency. The preferred embodiments are directed to such improvements.